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VLSI and Microelectronics Group


Faculty Members

1 Dr. Anu Mehra- Group Leader amehra@amity.edu
 2 Dr. Sujata Pandey spandey@amity.edu
3 Dr. Pradeep Kumar pkumar4@amity.edu
4 Mr. Lala Bhaskar lbhaskar@amity.edu
5 Ms. Nidhi Gaur ngaur@amity.edu
6 Mr. Ashutosh Gupta agupta5@amity.edu
7 Mr. Sunil Verma skumar34@amity.edu
8 Mr. Paurush Bhulania pbhulania@amity.edu
9 Mr. Sachin Rajput srajput@amity.edu
10 Shikha Bathla sbathla@amity.edu

Current Research Areas

  • Nanoscale Semiconductor Device modelling and simulation for implementation in circuit simulators
  • Organic photovoltaics (Design and Fabrication)
  • Design of Low power analog/ mixed signal VLSI Circuits (Using CAD/ EDA and its hardware realization)
  • Energy harvesting
  • Biomedical Electronics- Brain Computer Interface
  • Digital Design using VHDL/Verilog and System Verilog and implementation on FPGA
  • Universal Filter Design Using New Generation Active Building Blocks and Applications
  • Active Only Universal Filter Design Using New Generation Active Building Blocks
  • Development Analysis and Implementation of Noise Cancellation Algorithms by Adaptive Filtering
  • Power and delay optimization of Digital Circuit
  • Operational Amplifier Circuit Design for Signal Processing Units
  • Investigation of Tunnel FET and its applications
  • Organic LEDs and Polymer LEDs
  • Substrate coupling/ Mixed signal design
  • Reconfigurable ADC for low power application
  • Optimization of VLSI Architectures
  • Power reduction of Digital Circuits
  • Power Analog Amplifier Design
  • Photovoltaic Cell Analysis
  • Power Optimization of Processor Architecture

Some of the Current Research Problems

Focus: Nanoscale Semiconductor Device modelling and simulation for implementation in circuit simulators
Research Problem: Computational modelling of tunnelling field effect transistors (TFETs)
-(Dr. Sujata Pandey )
Research Problem: Quantum Mechanical modelling of nanoscale devices (Sub 22nm devices)
-(Dr. Sujata Pandey )
Research Problem: Computational modelling of wide bandgap devices
-(Dr. Sujata Pandey )
Research Problem: Design of Gallium Nitride based amplifiers and switches
-(Dr. Sujata Pandey )
Research Problem: Development of Sensing application of different nanowires
-(Dr. Sujata Pandey )
Research Problem: Computational modelling of semiconductor nanowires for ultrafast switching and optoelectronics devices
-(Dr. Sujata Pandey )
Research Problem: Development of Graphene based nanowires
-(Dr. Sujata Pandey )
Research Problem: Identification of Graded heterostructure FETs for THz generation
-(Dr. Sujata Pandey )
Focus: Organic photovoltaics (Design and Fabrication)
Research Problem: Design of organic LEDs with high efficiency
-(Dr. Sujata Pandey )
Research Problem: Reliability and statistical analysis of OLEDs
-(Dr. Sujata Pandey )
Research Problem: High efficiency Polymer based LEDs
-(Dr. Sujata Pandey )
Focus: Design of Low power analog/ mixed signal VLSI Circuits (Using CAD/ EDA and its hardware realization)
Research Problem: Development of low power architecture for data converters, memories and other digital circuits (Thermal and power modelling and analysis using CAD and EDA)
-(Dr. Sujata Pandey )
Research Problem: Development of reconfigurable circuits
-(Dr. Sujata Pandey )
Research Problem: CAD and Modelling of Nano electronic Digital and Analog/Mixed-Signal Circuits and Systems
-(Dr. Sujata Pandey )
Research Problem: Sub threshold and near threshold circuit design
-(Dr. Sujata Pandey )
Research Problem: Architectural implications of novel device technologies
-(Dr. Sujata Pandey )
Research Problem: SOC and NOC Design for different standard bus protocols for connecting on-chip IP, custom logic, and specialized functions
-(Dr. Sujata Pandey )
Focus: Energy harvesting
Research Problem: Energy harvesting from low frequency vibrations
-(Dr. Sujata Pandey )
Research Problem: Energy harvesting from motion
-(Dr. Sujata Pandey )
Research Problem: Energy scavenging from RF and microwaves
-(Dr. Sujata Pandey )
Research Problem: Development of energy harvesting techniques for wireless sensor nodes.
-(Dr. Sujata Pandey )
Research Problem: Hardware Development of integrated system for energy harvesting from multiple sources
-(Dr. Sujata Pandey )
Focus: Biomedical Electronics- Brain Computer Interface
Research Problem: Study and analysis of EEG signals.
-(Mr. Ashutosh Gupta )
Research Problem: Identifying various algorithm for the Classification of EEG Signals
-(Mr. Ashutosh Gupta )
Research Problem: Developing a novel method for interfacing brain with computer
-(Mr. Ashutosh Gupta )
Focus: Digital Design using VHDL/Verilog and System Verilog and implementation on FPGA
Research Problem: Design and Implementation of low power clock gated 64-bit ALU on ultra-scale fpga.
-(Mr. Ashutosh Gupta )
Research Problem: Design and Implementation of Power Efficient 10-Bit Dual Port SRAM
-(Mr. Ashutosh Gupta )
Research Problem: Power Efficient Digital design using Static Timing Analysis.
-(Mr. Ashutosh Gupta )
Focus: Analog Signal generation and processing
Research Problem: Designing of electronically tunable grounded to floating admittance converters employing minimum ABBs with no component matching constraints and their application in realization of floating resistor, inductor and capacitor.
-(Dr. Mayank Srivastava )
Research Problem: Active only grounded to floating admittance converter employing minimum no, of ABBs with no requirement of external passive resistance and electronically controllable scaling factor.
-(Dr. Mayank Srivastava )
Research Problem: Designing of generalized floating impedance/admittance circuits
-(Dr. Mayank Srivastava)
Focus: Universal Filter Design Using New Generation Active Building Blocks and Applications
Research Problem: Voltage mode universal filter design using current conveyors.
-(Dr Pradeep Kumar )
Research Problem: Current mode universal filter design using current conveyors
-(Dr Pradeep Kumar )
Research Problem: Voltage/Current mode filters design using translinear current conveyors.
-(Dr Pradeep Kumar )
Focus: Active Only Universal Filter Design Using New Generation Active Building Blocks
Research Problem: Multifunction active only universal filter design using current conveyor/translinear current conveyors
-(Dr Pradeep Kumar )
Focus: Development Analysis and Implementation of Noise Cancellation Algorithms by Adaptive Filtering
Research Problem: New model development for Adaptive Noise Cancellation using LMS algorithm.
-(Dr Pradeep Kumar )
Focus: Power and delay optimization of Digital Circuit
Research Problem: Investigation and implementation new techniques for power optimization for digital circuits and VLSI architecture.
-(Sachin Kumar Rajput )
Research Problem: Design of High Speed VLSI circuits using gating techniques.
-(Sachin Kumar Rajput )
Research Problem: Leakage and Power optimization in submicron region beyond 90nm using Lector technique
-(Sachin Kumar Rajput )
Research Problem: Low Power Digital circuits Design in sub-threshold region.
-(Sachin Kumar Rajput )
Research Problem: Low Power Low Voltage Dynamic FF TSPC Devide by N/N+1 counter.
-(Sachin Kumar Rajput )
Focus: Operational Amplifier Circuit Design for Signal Processing Units
Research Problem: Design of Operational Amplifier Circuits for signal processing in ADC.
-( Sachin Kumar Rajput )
Focus: Investigation of Tunnel FET and its applications
Research Problem: Investigation and modelling of TFET.
-( Sachin Kumar Rajput )
Focus: Organic LEDs and Polymer LEDs
Research Problem: Modeling and simulation of Organic LEDs and polymer LEDs for better efficiency, intensity and lifetime.
-(Ms. Shikha Bathla )
Focus: Substrate coupling/ Mixed signal design
Research Problem: noise sensor and digital switching for low power.
-(Neeru Agarwal )
Focus: Reconfigurable ADC for low power application
Research Problem: Power Scalable ADC whose power scales with resolution
-(Neeru Agarwal )
Focus: Optimization of VLSI Architectures
Research Problem: Design and Development of Algorithms for Finger Vein Recognition
-(Dr M.K.Dutta , Mr Manmohan Singh and Prof. Carlos M Travieso-Gonzalez ) Research Problem: Optimize performance and power consumption of VLIW architecture
-(Dr Anu Mehra )
Research Problem: Implementation and Optimization of Tomesulo Algorithm using HDL.
-(Dr Anu Mehra )
Research Problem: To optimize Booth algorithm for low power Multipliers.
-(Dr Anu Mehra )
Research Problem: Optimize Digital Architectures using Vedic components like dividers and multipliers
-(Dr Anu Mehra )
Focus: Power reduction of Digital Circuits
Research Problem: Examining new techniques of power reduction and applying to existing circuits
-(Dr Anu Mehra )
Research Problem: Leakage Current Minimization to reduce static power
-(Dr Anu Mehra )
Research Problem: Optimizing Delay and designing fast circuits for use in processors etc
-(Dr Anu Mehra )
Focus: Power Analog Amplifier Design
Research Problem: Differential matching in amplifiers
-(Dr Anu Mehra )
Research Problem: Maintaing of output signal and efficiency
-(Dr Anu Mehra )
Research Problem: To design area efficient Analog to Digital convertor using MUX.
-(Dr Anu Mehra )
Focus: Photovoltaic Cell Analysis
Research Problem: Charge Carrie Generation in Solar Cells
-(Dr Anu Mehra )
Research Problem: Addressing Light Absorption problems
-(Dr Anu Mehra )
Focus: Power Optimization of Processor Architecture
Research Problem: To design low power components for VLIW and RISC architectures to enhance the battery life.
-(Nidhi Gaur )
Research Problem: To design Low power ALU unit for Processor design.
-(Nidhi Gaur )
Focus: Design and Implementation of Optimized Real Time Heart Beat Analysis
Research Problem: Real time heart beat data acquisition.
-(Mr. Lala Bhaskar )
Research Problem: Wireless data transmission for data analysis.
-(Mr. Lala Bhaskar )
Research Problem: Classifying the data with Database
-(Mr. Lala Bhaskar)

Lab Infrastructure and Computing facility

Mentor Graphics HEP II- Vivado

Silvaco- ATLAS, BLAZE

COMSOL- MEMS module

ORCAD- Capture, PSPICE

FPGA Virtex IV boards- 2nos

Xilinx Z- Board- 2nos